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AT86RF232
from states TRX_OFF or PLL_ON by writing the command RX_AACK_ON. There is no
additional configuration required to receive IEEE 802.15.4 compliant frames when using
the Basic Operating Mode. However, the frame reception in the Atmel AT86RF232
Extended Operating Mode requires further register configurations, for details refer to
Section 7.2 .
The AT86RF232 receiver has an outstanding sensitivity performance of -100dBm. It
may be useful to manually decrease this sensitivity. This is achieved by adjusting the
synchronization header detector threshold using register bits RX_PDT_LEVEL
(register 0x15, RX_SYN). Received signals with an RSSI value below the threshold do
not activate the demodulation process.
Furthermore, it may be useful to protect a received frame against overwriting by
subsequent received frames.
A Dynamic Frame Buffer Protection is enabled with register bit RX_SAFE_MODE
(register 0x0C, TRX_CTRL_2) set, see Section 11.6 . The receiver remains in RX_ON
or RX_AACK_ON state until the whole frame is read by the microcontroller, indicated by
pin 23 (/SEL) = H during the SPI Frame Receive Mode. The Frame Buffer content is
only protected if the FCS is valid.
A Static Frame Buffer Protection is enabled with register bit RX_PDT_DIS
(register 0x15, RX_SYN) set. The receiver remains in RX_ON or RX_AACK_ON state
and no further SHR is detected until the register bit RX_PDT_DIS is set back.
9.1.4 Register Description
Register 0x15 (RX_SYN):
The register RX_SYN controls the blocking of receiver path and the sensitivity threshold
of the receiver.
Figure 9-2 . Register RX_SYN.
Bit
0x15
Read/Write
Reset value
Bit
0x15
Read/Write
Reset value
7
RX_PDT_DIS
R/W
0
3
R/W
0
6
R
0
2
R/W
0
5
reserved
R
0
1
RX_PDT_LEVEL
R/W
0
4
R
0
0
R/W
0
RX_SYN
RX_SYN
? Bit 7 - RX_PDT_DIS
The register bit RX_PDT_DIS prevents the reception of a frame during RX phase.
Table 9-1. RX_PDT_DIS.
Register Bits
RX_PDT_DIS
Value
0
1
Description
RX path is enabled
RX path is disabled
RX_PDT_DIS = 1 prevents the reception of a frame even if the radio transceiver is in
receive modes. An ongoing frame reception is not affected. This operation mode is
independent of the setting of register bits RX_PDT_LEVEL.
101
8321A – MCU Wireless – 10/11
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